IEEE

A Low Phase Noise PLL Design Based on Self-Injected Locking and In-Loop Mixing Technique

Abstract: In this letter, a combined technique of self-injection locking and in-loop mixing (SIL-MIX) is applied to a phase-locked loop (PLL) frequency synthesizer, which significantly reduces the ...
IEEE

A 5–10-GHz Quadrature Clock Generator With Open-Loop Quadrature Error Correction in 28-nm ...

Abstract: This letter introduces the design of a 4-phase quadrature clock generator (QCG) featuring digital automatic calibration. The QCG architecture comprises a ...